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Integrated Programmed Counter IC Chip Spartan-6 Family Overview XC6SL4-2TQG144C

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Integrated Programmed Counter IC Chip Spartan-6 Family Overview XC6SL4-2TQG144C

China Integrated Programmed Counter IC Chip Spartan-6 Family Overview XC6SL4-2TQG144C supplier

Large Image :  Integrated Programmed Counter IC Chip Spartan-6 Family Overview XC6SL4-2TQG144C

Product Details:

Place of Origin: TAIWAN
Brand Name: Xilinx
Certification: Original Factory Pack
Model Number: XC6SL4-2TQG144C

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Integrated Programmed Counter IC Chip Spartan-6 Family Overview XC6SL4-2TQG144C



XC6SL4-2TQG144C Xilinx Parogramm IC Chip Spartan-6 Family




• Spartan-6 Family:

• Spartan-6 LX FPGA: Logic optimized

• Spartan-6 LXT FPGA: High-speed serial connectivity

• Designed for low cost

• Multiple efficient integrated blocks

• Optimized selection of I/O standards

• Staggered pads

• High-volume plastic wire-bonded packages

• Low static and dynamic power

• 45 nm process optimized for cost and low power

• Hibernate power-down mode for zero power

• Suspend mode maintains state and configuration with multi-pin wake-up, control enhancement

• Lower-power 1.0V core voltage (LX FPGAs, -1L only)

• High performance 1.2V core voltage (LX and LXT FPGAs, -2, -3, and -4 speed grades)

• Multi-voltage, multi-standard SelectIO™ interface banks

• Up to 1,050 Mb/s data transfer rate per differential I/O

• Selectable output drive, up to 24 mA per pin

• 3.3V to 1.2V I/O standards and protocols

• Low-cost HSTL and SSTL memory interfaces

• Hot swap compliance

• Adjustable I/O slew rates to improve signal integrity

• High-speed GTP serial transceivers in the LXT FPGAs

• Up to 3.125 Gb/s

• High-speed interfaces


General Description


The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous Spartan families, and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input lookup table (LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1 slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, poweroptimized high-speed serial transceiver blocks, PCI Express® compatible Endpoint blocks, advanced system-level power management modes, auto-detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a lowcost programmable alternative to custom ASIC products with unprecedented ease of use. Spartan-6 FPGAs offer the best solution for high-volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components that enable designers to focus on innovation as soon as their development cycle begins. Summary of Spartan-6 FPGA


including: Serial ATA, Aurora, 1G Ethernet, PCI Express, OBSAI, CPRI, EPON, GPON, DisplayPort, and XAUI • Integrated Endpoint block for PCI Express designs (LXT) • Low-cost PCI® technology support compatible with the 33 MHz, 32- and 64-bit specification. • Efficient DSP48A1 slices • High-performance arithmetic and signal processing • Fast 18 x 18 multiplier and 48-bit accumulator • Pipelining and cascading capability • Pre-adder to assist filter applications • Integrated Memory Controller blocks • DDR, DDR2, DDR3, and LPDDR support • Data rates up to 800 Mb/s (12.8 Gb/s peak bandwidth) • Multi-port bus structure with independent FIFO to reduce design timing issues • Abundant logic resources with increased logic capacity • Optional shift register or distributed RAM support • Efficient 6-input LUTs improve performance and minimize power • LUT with dual flip-flops for pipeline centric applications • Block RAM with a wide range of granularity • Fast block RAM with byte write enable • 18 Kb blocks that can be optionally programmed as two independent 9 Kb block RAMs • Clock Management Tile (CMT) for enhanced performance • Low noise, flexible clocking • Digital Clock Managers (DCMs) eliminate clock skew and duty cycle distortion • Phase-Locked Loops (PLLs) for low-jitter clocking • Frequency synthesis with simultaneous multiplication, division, and phase shifting • Sixteen low-skew global clock networks • Simplified configuration, supports low-cost standards • 2-pin auto-detect configuration • Broad third-party SPI (up to x4) and NOR flash support • Feature rich Xilinx Platform Flash with JTAG • MultiBoot support for remote upgrade with multiple bitstreams, using watchdog protection • Enhanced security for design protection • Unique Device DNA identifier for design authentication • AES bitstream encryption in the larger devices • Faster embedded processing with enhanced, low cost, MicroBlaze™ soft processor • Industry-leading IP and reference designs


Spartan-6 FPGA Feature Summary

Table 1: Spartan-6 FPGA Feature Summary by Device

Device Logic cells Slices Flip-Flops Max Distributed RAM(kb) DSP48A1 Slices 18 Kb Max (Kb) CMTs Memory Controller Blocks (Max) Endpoint Blocks for PCI Express Maximum GTP Transceivers Total I/O Banks Max User
XC6SLX4 3,840 600 4,800 75 8 12 216 2 0 0 0 4 132
XC6SLX9 9,152 1,430 11,400 90


32 576 2 2 0 0 4 200
XC6SLX16 14,579 2,278 18,244 136 32 32 576 2 2 0 0 4 232
XC6SLX25 24,051 3,758 30,064 229 38 52 936 2 2 0 0 4 266
XC6SLX45 43,661 6,822 54,576 401 58 116 2088 4 2 0 0 4 358
XC6SLX75 74,637 11,662 93,296 692 132 172 3096 6 4 0 0 6 408
XC6SLX100 101,261 15,822 125,676 976 180 268 4824 6 4 0 0 6 480
XC6SLX150 147,443 23,038 184,304 1355 180 268 4824 6 4 4 0 0 6
567XC6S LX25T 24,051 3,758 30,064 229 38 52 936 2 2 1 2 4 250
XC6SLX45T 43,661 6,822 54,576 401 58 116 2088 4 2 1 4 4 296
XC6SLX75T 74,637 11,622 93,296 692 132 172 3096 6 4 1 8 6 348
XC6SLX100T 101,261 15,822 126,576 976 180 268 4824 6 4 1 8 6 498
XC6SLX150T 147,443 23,038 184,304 1355 180 268 4824 6 4 1 8 6 540


Notes: 1. Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.

2. Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.

3. Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.

4. Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.

5. Each CMT contains two DCMs and one PLL.


Spartan-6 FPGA Device-Package Combinations and Available I/Os


Table 2: Spartan-6 Device-Package Combinations and Maximum Available I/Os

Integrated Programmed Counter IC Chip Spartan-6 Family Overview XC6SL4-2TQG144C


1. There is no memory controller on the devices in these packages.

2. Memory controller block support is x8 on the XC6SLX9 and XC6SLX16 devices in the CSG225 package. There is no memory controller in the XC6SLX4.

3. These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.

4. These packages support two of the four memory controllers in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and XC6SLX150T devices.


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