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|FEATURES:||Designed And Qualified For Industrial Level||FEATURES2:||8-bit Serial Input|
|FEATURES3:||8-bit Serial Or Parallel Output||FEATURES4:||Storage Register With 3-state Outputs|
|FEATURES5:||Shift Register With Direct Clear||FEATURES6:||100 MHz (typ) Shift Out Frequency|
|FEATURES7:||Output Capability: – Parallel Outputs; Bus Driver – Serial Output; Standard||FEATURES8:||ICC Category: MSI.|
8 Pin Robert Noyce Integrated Circuit Chip 74HC595D Parallel Out Shift Register
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typ) shift out frequency
• Output capability: – parallel outputs; bus driver – serial output; standard
• ICC category: MSI.
Serial-to-parallel data conversion
• Remote control holding register.
The 74HC/HCT595 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The “595” is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks.
Data is shifted on the positive-going transitions of the SHCP input. The data in each register is transferred to the storage register on a positive-going transition of the STCP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7’) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.
1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑(CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC − 1.5 V.
|Q0 to Q7||15, 1 to 7||parallel data output|
|Q7’||9||serial data output|
|MR||10||master reset (active LOW)|
|SHCP||11||shift register clock input|
|STCP||12||storage register clock input|
|OE||13||output enable (active LOW)|
|DS||14||serial data input|
|VCC||16||positive supply voltage|
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.