TP3094V Integrated Circuit Chip Electronics Ic Chip Quad PCM Codec / Filter

TP3094 COMBO® Quad PCM Codec/Filter

General Description

  The TP3094 is a monolithic PCM Codec and Filter device implemented using a digital signal processing architecture. It provides four voice channels, combining transmit bandpass and receive low pass channel filters with companding Alaw or m-law PCM encoders and decoders. The device is fabricated using National’s advanced CMOS process. The device includes anti-aliasing filters and sigma-delta converters dedicated to each channel, and by a common signal processing unit which performs all the remaining filtering and processing for the four channels. The TP3094 includes a flexible PCM digital interface, which allows the device to be connected to PCM busses of different formats. It can also be connected with other TP3094 devices in a cascade fashion, for a system with up to 128 POTS interfaces (when a 2.048MHz PCM bus is used).

Features

• Handles four voice channels

• Complete Codec and Filter system including:

- Transmit and receive channel filters

- A-law or m-law companding encoder/decoder

• Power down mode for low power consumption

• Compatible to standard time division multiplexed PCM bus

- 8 bit mode, frame signal from external reference

- 32 bit mode, internal TSA, with consecutive TS

• Up to 128 channels (32 devices) can be cascaded

• Programmable functions (common for all 4 channels):

- A-law or m-law

- Single MCLK clock,automatically selectable

from 8.192MHz, 4.096MHz, 2.048MHz and 1.536/1.544MHz

- Digital and Analog loopback test modes

• Designed for CCITT and LSSGR applications

• Single +5V power supply

• 44 lead PLCC surface mount package

• Maximize line card circuit density

• Use in Central Office, Loop Carrier,

and PBX equipment subscriber line and trunk cards

• Wide operating temperature range -40°C to 85°C

Power Initialization

When power is first applied to the device, poweron reset circuitry initializes the device and places it in the power down state. All non-essential circuits are de-activated. PCM output DX and analog outputs VRO0-3 are placed in the high impedance state, while FSX1 and FSR1 outputs are held low (in case 32-bit mode is selected). In the power down mode, power consumption is reduced to a minimum, typically 2mW. The device will remain in this state as long as no MCLK is applied and no Frame Signal is applied (just FSX0 and FSR0 in case of 32-bit mode). For each channel, when the PDN input is not active, MCLK is applied, and a FS (receive or transmit) pulse is running, the device enters the active power up mode. The MCLK frequency is detected with any available FS signal; the clock rate detection may last for up to 4ms, after which the device is ready for powering up. Analog and PCM output signals will be available after a few frames; it will take about 100ms until the first activated channel is fully functional. The device will only power up when at least one of the FS signals and the MCLK signal are in a valid frequency ratio.

Timing Diagrams