Anterwell Technology Ltd.
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Feature 1: | Octal Bidirectional Bus Interface | Feature 2: | Non-inverting 3-state Outputs |
---|---|---|---|
Feature 3: | Multiple Package Options | Feature 4: | Complies With JEDEC Standard No. 7A |
ESD Protection 1: | HBM EIA/JESD22-A114-B Exceeds 2000 V | ESD Protection 2: | MM EIA/JESD22-A115-A Exceeds 200 V |
High Light: | integrated circuit ic,integrated circuit components |
1. General description
The 74HC245; 74HCT245 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL).
The 74HC245; 74HCT245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The 74HC245; 74HCT245 features an output enable input (OE) for easy cascading and a send/receive input (DIR) for direction control. OE controls the outputs so that the buses are effectively isolated.
The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.
2. Features
■ Octal bidirectional bus interface
■ Non-inverting 3-state outputs
■ Multiple package options
■ Complies with JEDEC standard no. 7A
■ ESD protection:
◆ HBM EIA/JESD22-A114-B exceeds 2000 V
◆ MM EIA/JESD22-A115-A exceeds 200 V
■ Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Quick reference data
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Symbol | Parameter | Conditions | Min | Typ | Max | Unit |
Type 74HC245 | ||||||
tPHL, tPLH |
propagation delay An to Bn or Bn to An |
CL = 15 pF; VCC =5V |
- | 7 | - | ns |
CI | input capacitance | - | 3.5 | - | pF | |
CI/O | input/output capacitance | - | 10 | - | pF | |
CPD |
power dissipation capacitance per transceiver |
VI = GND to VCC | [1] - | 30 | - | pF |
Type 74HC245 | ||||||
tPHL, tPLH |
propagation delay An to Bn or Bn to An |
CL = 15 pF; VCC =5V |
- | 10 | - | ns |
CI | input capacitance | - | 3.5 | - | pF | |
CI/O | input/output capacitance | - | 10 | - | pF | |
CPD |
power dissipation capacitance per transceiver |
VI = GND to VCC − 1.5 V |
[1] - | 30 | - | pF |
[1] CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi × N + ∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
∑ (CL × VCC2 × fo) = sum of outputs.
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